RS485 brief introduction

RS485 is half-duplex communication. Half-duplex communication means that the channel can only be receiving or transmitting at a time. RS485 is characterized by supporting multi-node transmission, long transmission distance, and strong anti-interference ability. RS485 can connect multiple 485 devices, and the signal rate can reach 10MBPS. The voltage difference between the two lines AB is used to determine whether it is logic level 1 or logic level 0. When the voltage difference between AB is greater than 200mv, it is high level 1, and when it is less than 200MV, it is logic level 0. Generally, resistors 120R are connected at the first and last ends. Its function is to match impedance and eliminate signal reflection.

RS485 hardware circuit design

RS485 circuit design can be divided into isolation type and separate isolation type. The figure below is a non-isolated circuit. The B terminal is connected to GND and pulled down, and the A terminal is high level through the pull-up resistor to ensure that the voltage difference between A and B is greater than 200MV. The DE and RE pins enable transmission and reception. When RE is low, reception is enabled, and when DE is high, transmission is enabled. In applications, the two are generally connected together and controlled through the IO port (RS485_EN), because The chip is either receiving or transmitting, so before sending data, the RS485_EN signal is given a high level, and when receiving data, it is given a low level.

RS485 automatic sending and receiving circuit hardware design

The difference between the automatic transceiver circuit and the ordinary 485 circuit is that there is one more transistor to control the enable pin of the 485. R9 current-limiting resistor, usually 4.7K, and R8 pull-up resistor, usually 4.7K, cause the enable pin to be pulled up when the transistor is not conducting.

When receiving data: The receiving data pin is the first pin of the chip, which is the network label RS485_RX. During the process of receiving data, the RS485_TX pin remains high, VGS is high, and the NPN transistor Q1 is turned on, RE and The connected pin of DE is pulled down to GND through the transistor. At this time, the reception is enabled and is in the receiving state.

When sending data: The sending data pin is RS485_TX, and RS485_TX should send 1. The transistor is turned on, the levels of RE# and DE are low, and the RS485 transceiver chip is not turned on. Since 485 is high level under normal conditions, the data is high at this time. , when RS485_TX sends 0, the transistor is not turned on. At this time, the transmit enable of the 485 transceiver chip is high and effective. Since DI has been pulled down to GND, the data sent is 0. In this way, automatic sending and receiving of 485 is realized.

Send detailed analysis:

RS485_TX sends 1, VGS is high level, the NPN transistor is on, the enable pin is low level, the sending is invalid, the reception is enabled, and it is in the receiving state. Since the AB pin of the SP3485 chip is in a high impedance state, R4 pulls A High, R5 pulls B low, so AB transmits 1. That is, when RS485_TX sends 1, the AB pin sends 1.

RS485 interface lightning protection circuit design

Interface protection circuit

L1 is a common mode inductor. The common mode inductor attenuates common mode noise and enhances anti-interference ability. Generally, 120Ω/100MHz is selected. The function of the C3 capacitor is to separate the interface ground and the digital ground. Generally, 1000pf is selected. In order to meet the EMC protection requirements, the differential mode signal is 2KV and the common mode signal is 6KV. A gas discharge tube, thermistor, and TVS tube will be reserved at the interface to form a protection circuit.

gnd design of RS485 interface circuit PCB

The protective devices at the dotted line should be as close to the interface as possible and placed compactly and neatly. Protective devices should be removed first and then filter devices should be placed.