[Processor model]：T113-i
[Processor frequency]：1.2GHz
[Memory capacity]：256MB
[Storage capacity]：256MB
[Product size]：45*35*3.6mm
[Product weight]：15±1g
[Introduction]：Ebyte ECK30-T13IA series core board is carefully designed based on Allwinner's T113-i processor. It is a low-cost, low-power, cost-effective, and highly reliable industrial-grade embedded core board with stamp hole connection. It can be widely used in industrial control, HMI, IoT and other fields.
| Function | quantity | Function description |
| CPU | 1 |
T113-i； Dual-core ARM Cortex-A7@1.2GHz； RISC-V CPU； HiFi4 DSP； |
| MEM | 1 |
On-board DDR3 SDRAM, 16-bit wide, 256MB/512MB/1GB optional; |
| FLASH | 1 |
On-board 8GB eMMC / On-board 256MB SPI NAND FLASH optional; |
| DISPLAY | 1 |
Parallel RGB 24-bit color output, supporting up to 1920×1080@60fps; Dual-channel LVDS output, supporting up to 1920×1080@60fps; 4-lane MIPI DSI, supporting up to 1920×1200@60fps; Note: Some of the I/Os of the above display interface are multiplexed and cannot be used at the same time; serial RGB output supports up to 800×480@60fps; |
| CSI | 1 |
8-bit parallel digital camera interface, supports 1080P@30fps, maximum 148.5MHz pixel clock; |
| CVBS IN | 2 |
1 CVBS decoder, supports NTSC and PAL formats, 10-bit video ADC; |
| CVBS OUT | 1 |
Supports NTSC and PAL formats, 10-bit video DAC; |
| Audio Codec | 1 |
2-channel DAC, sampling rate 8KHz~192KHz; 3-channel ADC, sampling rate 8KHz~48KHz; 3 MIC IN, 1 LINE IN, 1 FM IN; 1 differential LINE OUT, 1 Headphone OUT; |
| EMAC | 1 |
Support RMII/RGMII interface (10/100/1000Mbps); |
| SMHC | 2 |
Support SD3.0, SDIO3.0, MMC5.0 protocols; SDC0: 4-bit data bus (recommended as backplane Micro SD function); SDC1: 4-bit data bus; Note: SDC2 is not led to the stamp hole and is used to connect eMMC or FLASH memory chips on the board; |
| USB DRD | 1 |
Complies with USB2.0 standard and supports USB HOST and USB Device functions; |
| USB HOST | 1 |
Comply with USB2.0 standard and support USB HOS function; |
| TWI(I2C) | 4 |
Supports standard mode (100Kbps) and high-speed mode (400Kbps); |
| SPI | 1 |
Supports SPI mode and DBI (Display Bus Interface) mode; Supports Master Mode, Slave Mode, and 1 chip select signal; Supports up to 100MHz operating frequency; |
| UART | 6 |
Maximum 4Mbps baud rate (64MHz APB clock), supports hardware or software flow control; |
| PWM | 8 |
0~100% adjustable duty cycle, supports output and input capture, output frequency is 0~24MHz or 100MHz; |
| GPADC | 2 |
12-bit SAR type A/D converter with sampling frequency up to 1MHz; |
| TPADC | 4 |
12-bit SAR type A/D converter, sampling frequency up to 1MHz, supports 4-wire resistive touch screen; |
| LRADC | 1 |
6-bit A/D converter, sampling frequency up to 2KHz, supports hold keys and general keys; |
| LEDC | 1 |
Supports 1024 LED serial connections, LED data transmission rate up to 800Kbps; |
| PCM/I2S | 3 |
Support full duplex, sampling rate 8KHz~384KHz; |
| DMIC | 1 |
Supports up to 8 channels, sampling rate 8KHz~48KHz; |
| OWA | 1 |
One Wire Audio, compatible with S/PDIF protocol; |
| CIR | 2 |
Contains CIR TX and CIR RX, which can be controlled remotely through infrared; |
| CAN | 2 |
Support CAN 2.0A and CAN 2.0B protocols; |
| JTAG | 3 |
Contains ARM, RISC-V and HiFi4 DSP JTAG; |
| GPIO | 79 |
Software configures GPIO function and supports interrupt input; |
