I2C vs SPI: Choosing a Serial Peripheral Bus

Key Takeaways

• I2C trades pin count for bus management: two wires carry many addressed targets, but pull-ups set the clock ceiling.
• SPI trades pins for speed: one chip select per target, no acknowledgement, and clock rates I2C cannot reach.
• Clock stretching lets an I2C target pause the master; a host that does not support it can fail intermittently.
• Size pull-ups against total bus capacitance and the target clock, not against a single device datasheet.
• Multi-master arbitration is defined in I2C; SPI is single-master by construction.

1. What Is I2C?

I2C is a two-wire synchronous serial bus that addresses each target with a unique 7-bit address on a shared pair of lines.

Serial data (SDA) and serial clock (SCL) run to every device on the bus, each with its own pull-up resistor, so no device needs a dedicated connection to the host.

• Shared two-wire bus: both lines are open-drain, so any driver can only pull a line low and the pull-up restores it.
• Address-based selection: each target answers to its own address, so adding a device costs an address slot rather than a pin.
• Receiver-driven acknowledgement: the receiver pulls SDA low after every byte, which makes a missing or mis-addressed device visible.
• Multi-master arbitration: two masters can start at once, and the one that loses drops out without corrupting the frame.

2. How Does an I2C Transaction Work?

An I2C transaction follows the same phases whatever the target does with the bytes.

1. Start condition. The master pulls SDA low while SCL is high, a pattern reserved for signalling, not data.
2. Address and direction bit. The master shifts out a 7-bit address plus one read/write bit; a target that does not match stays silent.
3. Acknowledge. On the ninth clock the addressed target pulls SDA low to confirm it heard the address.
4. Data and acknowledge cycles. Each byte is followed by an acknowledge bit, so a device that stops responding is caught inside the transfer.
5. Stop condition or repeated start. The master releases SDA while SCL is high to end the frame, or issues a repeated start.
6. Clock stretching. A target that needs more time holds SCL low, and the master waits before clocking the next bit.

3. What Is SPI?

SPI is a four-wire synchronous bus where the master generates the clock and selects one target with a dedicated chip select line.

SPI sits at the same physical and link layer as I2C, but it multiplexes devices in space rather than by address.

• Chip select per target: the master drives one chip select low to open a conversation with one device, and the others ignore the clock.
• Master-generated clock: the clock runs for the whole frame, so no target can hold it back.
• Simultaneous shift: data leaves on one line and arrives on the other at the same time, which makes the link full duplex.
• No acknowledgement, and a mode to match: there is no address and no acknowledge bit, so a wrong device or a wrong mode is silent rather than reported; per the SPI mode convention, both ends must agree on clock polarity and phase.

4. I2C vs SPI: What Is the Difference?

The two buses differ mainly in what they trade away: I2C spends address overhead to save pins, while SPI spends pins to save time.

The decision rule: choose I2C when several slow devices must share few pins; choose SPI when one or two devices need sustained throughput and an extra pin costs less than bus overhead.

5. Configuration and Key Parameters

Both buses have parameters that are easy to copy and hard to justify later, so match them to the bus you built.

• Pull-up value: per the I2C-bus specification, roughly 400 pF caps the standard and fast modes, and 4.7 kohm suits a short 3.3 V bus.
• Rise time against clock rate: the rising edge must settle inside the clock period, so a bus that passes at 100 kHz can fail at 400 kHz.
• Address collisions: a duplicate 7-bit address makes two devices answer together; 10-bit addressing extends the map, but host support is uneven.
• Clock stretching support: some hosts and DMA engines ignore the clock line, so a target that stretches will stall the bus.
• Chip-select budget: each SPI device costs one GPIO, and running out of pins often pushes a design back towards I2C.
• Mode mismatch: clock polarity and phase must match on both ends, and a mismatch returns shifted bits that look like a wiring fault.
• Series resistors and level shifting: a small series resistor damps edges, and a level shifter is needed when a 5 V device shares a 3.3 V bus.
• Trace length and stubs: long traces add capacitance and reflections, which lower the usable clock before any device misbehaves.
• Shared or separate bus for a noisy load: a load that switches large current is easier to isolate on its own bus.

6. When to Use I2C and When Not To

Good fit for I2C

• Several low- to medium-speed devices such as sensors, EEPROM and port expanders, where pin count matters more than throughput.
• Designs that must add a device without a new trace, where an address slot is cheaper than a GPIO.
• Boards where the signal lines are short and capacitance stays under the standard-mode ceiling.

Good fit for SPI

• Radios, memory and converters that move long register bursts and benefit from a continuous master clock.
• Point-to-point links where one device needs the fastest clock both ends allow.
• Links that must send and receive at the same time, which the shared two-wire bus cannot do.

Poor fit for I2C

• High-throughput links, where address, acknowledge and clock-stretch overhead costs time on every byte.
• Hosts whose driver or DMA block ignores clock stretching, which makes the bus unreliable.
• Long, noisy cable runs, where the pull-up and the single-ended edges are the limiting factor.

Poor fit for SPI

• Buses with many devices, where chip-select fan-out and extra traces dominate the layout.
• Designs with no spare GPIO, where each added device needs its own select line.
• Noisy environments, where the absence of acknowledgement hides a dropped frame.

7. Real-World Applications

In industrial, energy and building products the two buses usually appear together rather than as competitors: a host keeps a short I2C bus for its sensors and a separate SPI bus for its radio. A radio draws current in bursts, so keeping its clock and chip select away from the pulled-up sensor lines avoids coupling noise into a bus with no acknowledgement margin.

Among Ebyte modules, SPI is the usual attach for radio parts. The E22-400M22S pairs a Semtech SX1268 with an SPI interface, covers 410 to 493 MHz at 22 dBm, and lists a 7 km figure, while the E22-900M30S uses a Semtech SX1262 on 868 and 915 MHz at 30 dBm with a 12 km range.

For a smaller footprint, the E04-400M16S is an ultra-small patch-type module on the STMicroelectronics S2-LP at 433 and 470 MHz with SPI, and the E07-400M10S, based on the TI CC1101, gives 410 to 450 MHz at 10 dBm and a 1.5 km figure.

Modules that combine interfaces sit between the two worlds: the E70-400M14S1B, built on the TI CC1312R, exposes UART, I2C and SPI next to its radio. Antenna choice and feed routing account for more field failures than the bus choice does.

8. FAQ: I2C and SPI in Practice

Q1: What is the main difference between I2C and SPI?

I2C shares two wires across every device and selects each by address, while SPI gives each device its own chip select and runs at the clock the master sets. I2C saves pins and supports multi-master arbitration; SPI is simpler, faster and has no addressing overhead.

Q2: Why does my I2C bus stop working when I add another device?

Adding a device changes either the address map or the bus capacitance:

• Bus silent after a new part -> check its address for a duplicate.
• Fails at 400 kHz but passes at 100 kHz -> lower the pull-up value.
• One device holds SDA low -> check whether it released the line after a reset.

Q3: How do I choose the pull-up resistor value for I2C?

Choose the pull-up from the bus capacitance and the clock you intend to run. Per the I2C-bus specification, roughly 400 pF of total capacitance is the limit at standard and fast modes, and 4.7 kohm suits a short 3.3 V board.

Q4: What is clock stretching and why does it matter?

Clock stretching is an I2C target holding the clock line low to pause the master while it prepares data or clears a register. The bus cannot advance until the target releases the line, so a host that does not support stretching can lose bytes intermittently.

Q5: Can I use an I2C sensor and an SPI radio on the same host?

Yes, and it is the common arrangement. The I2C sensor shares two wires with any other addressed device, while the radio takes the SPI bus and one chip select pin. Keep the buses separate if the radio draws large current bursts.

Q6: Why does an SPI device return shifted or all-zero data?

Shifted or zero data points to the clock and the chip select, not the data lines:

• Data shifted by a bit -> match the host CPOL and CPHA to the device.
• All zeros -> confirm the chip select is asserted low during the transfer.
• Correct first byte then corruption -> shorten the trace.

9. Pre-Flight Checks Before You Route the Bus

1. Count the devices and the spare pins first, because that count decides the bus more often than the clock rate.
2. Add up the bus capacitance and pick the pull-up from it, then confirm the rise time inside the clock period.
3. Check that the host driver honours clock stretching, and that no two I2C targets share an address.
4. For every SPI target, confirm the chip select, the mode and a ground return shared with the host.
5. If a device draws current in bursts, give it its own bus rather than sharing the sensor lines.