Electrostatic Protection: On-Chip vs System-Level ESD

Key Takeaways

• On-chip electrostatic protection is rated by component models and covers handling and assembly, with the part unpowered.
• System-level electrostatic protection is rated by IEC 61000-4-2 and covers a powered product at its connectors and enclosure.
• A chip clamp sits at the pin, not at the connector, so it cannot protect the interface a cable reaches.
• The designer adds the interface clamp, its series impedance and a defined ground return path.
• Verification means the product keeps working at a stated IEC 61000-4-2 level, not that one component survived.

1. What Is On-Chip Electrostatic Protection?

On-chip electrostatic protection is the clamp built into a chip and its assembly process to survive a discharge during handling and manufacturing.

The clamp is part of the die and the package, not an accessory added later. Every part is handled, packed, placed and soldered before it reaches a board, and each step can deliver a charge into a pin.

Core characteristics

• Described by component models: the human body model (HBM), the charged device model (CDM) and the machine model (MM) each describe a charged object discharging into a pin of an unpowered part. The number belongs to the component, not the product.
• A clamp on every pin: each pin has a protection device to the supply rails and to ground that shunts current away from the gate oxide, then releases the pin for normal signalling.
• A survival criterion: passing means the clamp held and the die stayed intact. It says nothing about the board, the connector or the enclosure.

2. How Is On-Chip Protection Specified, and What Does It Cover?

On-chip protection is specified by stressing a bare component against a defined discharge model, and it covers the pin while the part is unpowered.

1. A protection structure is added to the pin. A clamp is connected between the pin and the supply rails and ground, offering a low-impedance path that stays inactive in normal use, but a clamp strong enough for a hard event adds capacitance and leakage.
2. The model defines the waveform. The human body model discharges a charged capacitor through a resistor into a pin, approximating a person touching a device. The charged device model charges the part itself and discharges it to ground.
3. The part is stressed unpowered. No supply is applied and no firmware runs during the test, which matches a handling bench or an assembly line.
4. The clamp turns on and diverts the current. During the event the clamp conducts and routes the discharge to the rails or ground instead of through the gate oxide.
5. The rating stops at the pin. It does not describe a discharge that arrives at a product connector, travels through a cable and exits through the enclosure.
6. The clamp must not disturb the signal. On a fast interface the capacitance and leakage of the protection device, rather than the discharge rating, often decide how much protection can be built in.

3. What Is System-Level Electrostatic Protection?

System-level electrostatic protection is the clamp and filtering a finished product needs at its connectors and enclosure to survive a discharge while operating.

The event differs in every way that matters: where it enters, what it travels through, and whether the product is running. The chip clamp is not at the connector and is not specified for this condition, so protection has to be added at the interface.

Core characteristics

• A different entry point: the discharge arrives at an accessible connector, a case seam or a metal part, a path outside the silicon.
• A path through the product: current flows in through the connector, across the board, and often back through the enclosure or the cable shield. The return is part of the design.
• A powered, operating condition: the disturbance is applied while the product is powered and running, so the protection must work without disturbing the signals it sits on.
• A different success criterion: the product keeps working through and after the event, rather than a component merely surviving it.

4. On-Chip vs System-Level: What Is the Difference?

The two protections answer different questions: one asks whether a component survives manufacturing, the other asks whether a product survives the field.

The decision rule: treat the on-chip rating as coverage for handling and assembly only, and add a system-level clamp at every interface a person or a cable can reach once the product is powered in the field.

5. Key Parameters and Where They Bite

Every line here is a place where the division of responsibility is decided in practice.

• Clamp turn-on voltage against the pin's absolute maximum: set the external clamp to conduct below the pin's limit and above the highest normal signal, or the pin is exposed or the signal clips.
• Parasitic capacitance on a high-speed line: a larger clamp carries more capacitance, which rounds edges and closes the signal eye, so pick the smallest device that handles the stated current.
• Series impedance and signal integrity: a small series resistor or ferrite limits the current reaching the chip, but too much attenuates the signal or adds delay.
• Ground return impedance at the connector: keep the return short and low impedance, because current forced through the signal ground raises the local ground into a disturbance the clamp cannot stop.
• Creepage and clearance: the spacing between conductors sets how much voltage is held off before an arc, and on a high-voltage input spacing often limits before the clamp does.
• Isolated compared with non-isolated interfaces: an isolated port gives the discharge no direct path into the low-voltage side, while a non-isolated port relies on the clamp and a short return.
• Verification at a stated level: verify against IEC 61000-4-2 at a stated level, such as 8 kV contact discharge, with the product powered, and record the cable arrangement.
• Handling controls in production: component ratings assume a controlled assembly area with ESD-safe benches, wrist straps, ionisers and packaging.

6. When to Rely on Which

Good fit for the on-chip rating alone

• Board-level links that never leave the enclosure and are never touched by a user.
• Components assembled in a controlled area with documented handling controls.
• Signals that are not referenced to an external ground and never leave the board.

Good fit for added system-level protection

• Any connector, button or metal part that a user can touch on an installed unit.
• Cables that leave the cabinet, the panel or the building.
• Field interfaces such as RS485 ports, antenna connectors and power inlets.

Poor fit for relying on the chip rating alone

• Field-installed units with exposed connectors.
• Units with an unconnected or high-impedance ground return.

Poor fit for over-clamping

• High-speed interfaces where the added capacitance closes the signal eye.
• Low-power signal lines where clamp leakage disturbs the reading.
• Space-limited connectors where the clamp cannot sit close to the entry point.

7. Real-World Applications

In industrial IoT, energy and building installations, the split between component protection and product protection appears as a design habit. The chip is chosen with a known component rating, and every interface a technician can touch is protected again at the board edge.

Ebyte devices sit on both sides of that pattern. The E15-LW-T1, an industrial mini PCI-e adapter test board for E106 series SX1302 and SX1303 LoRaWAN gateway modules across 230 MHz to 915 MHz bands, is listed with built-in ESD protection at interface level. The E90-DTU(400SL30P), a 1 W industrial wireless digital radio on 433 MHz based on the SX1262/SX1268, is listed with electrostatic discharge anti-interference level 4, fast transient level 4 and surge impact level 3 protection, a product-level claim rather than a component one.

For interfaces that reach a panel, the working parts matter as much as the modules. The E90-DTU(400SL22) is an industrial SX1268-based DTU with dual RS232 and RS485 ports, 22 dBm, up to 5 km and a wide 8-28 V DC input, so both the serial port and the supply input are candidates for an external clamp. The AM31-12W12V switching supply module and the AM11-12W12C offer safety isolation, so the isolation barrier is already part of the discharge path design. The MA01-AXCX4020 and the E831-RTU(8080T-485) put Modbus RTU IO on an RS485 trunk over an 8-28 Vdc supply, with relay outputs and dry-contact inputs at the edge of the enclosure.

One detail is consistently underestimated: the protection at a connector is only as good as its return path. A clamp placed far from the entry point, or returned through the signal ground, does much less than its part number suggests.

8. FAQ: Electrostatic Protection in Practice

Q1: Is on-chip ESD protection enough for a finished product?

No. An on-chip clamp is rated for a component-level discharge during handling and assembly, with the part unpowered. It does not cover a discharge at a product connector with the board powered and cabling attached. That gap is closed by adding a system-level clamp at the interface.

Q2: What is the difference between HBM and IEC 61000-4-2?

The human body model describes a charged person discharging into a pin of an unpowered component during manufacturing. IEC 61000-4-2 describes a discharge into a finished product while it is powered and operating. One rates the part, the other rates the product.

Q3: Why does my device reset when someone touches the connector?

A reset on contact points to a discharge path that has no clamp at the interface.

• Reset when a cable is plugged or unplugged -> add a TVS clamp and series impedance at that connector.
• Reset when a person touches the enclosure seam -> review the ground return and the enclosure bonding.
• Damage on the RS485 or antenna port -> verify isolation and review creepage and clearance.

Q4: Where should I add external clamping?

Add the clamp as close as possible to the point where the discharge enters, normally the connector. Keep the return path short so current does not flow through the signal ground. A TVS plus a small series impedance shares the energy and limits what reaches the chip.

Q5: How do I verify system-level electrostatic protection?

Apply the IEC 61000-4-2 disturbance at a stated level, such as 8 kV contact discharge, with the product powered and operating. Pass means the product keeps working after the event, not that a component merely survives. Record the level and the cable configuration used.

9. Pre-Flight Checks Before You Rely on a Chip Rating

1. Confirm what the rating covers. Ask whether the number is a component model rating or a system test result, and confirm it applies to the pin rather than to the product.
2. Map every accessible interface. List each connector, seam, button and metal part of a powered unit, and treat each as an entry point that needs its own clamp and return.
3. Size the clamp against the pin. Check the turn-on voltage against the pin's absolute maximum and the capacitance against the rise time of the signal before placing the part.
4. Verify the return path. Keep the discharge current out of the signal ground, and place the clamp as close to the entry point as the layout allows.
5. State the verification level. Define the IEC 61000-4-2 level, such as 8 kV contact discharge, with the product powered, and record the cable arrangement used.