In the application of single-chip microcomputer, communication protocol is an indispensable part. The communication between the host computer and the lower computer, the single-chip computer and the single-chip computer, and the single-chip computer and the peripheral modules all need the communication protocol to realize information exchange and resource sharing. Due to the different transmission rates, electrical characteristics, and reliability requirements between devices, many types of communication protocols suitable for different situations have also been produced, and are widely accepted and used. In fact, the most frequently used ones are as follows:


They are called Universal Asynchronous Receiver and Transceiver and Universal Synchronous Asynchronous Transceiver respectively. The speed is not fast and can be full duplex. The structure is generally composed of a baud rate generator, a UART/USART transmitter, and a UART/USART receiver. There are two lines on the hardware. One by one.

2. I2C (IIC)

Bidirectional, two-wire, serial, multi-master interface standard. The speed is not fast, half-duplex, synchronous interface, with bus arbitration mechanism, very suitable for short-range frequent data communication between devices, and can realize device networking.

Bus arbitration: line AND, whoever sends 0 will succeed in arbitration.

3. SPI

High-speed synchronous serial port, high-speed, full-duplex, independent transceiver, synchronous interface, can realize the interconnection of multiple SPI devices, hardware 3~4 lines; it is also common to all SPI-based devices, they are SDI (data input) , SDO (data output), SCK (clock), CS (chip select).

4. USB

High-speed synchronous serial port, high-speed, full-duplex, composed of host, hub and device. The device can be connected with the lower hub to form a star structure. A USB transmission line is composed of four lines: ground line, power line, D+ and D-. D+ and D- are differential input lines, which use a voltage of 3.3V. Data is transmitted in the USB line from low to high.

5. CAN

It adopts two-wire transmission, and the two wires are used as CAN_H and CAN_L respectively, and the terminal is equipped with a 120Ω resistance. When receiving the bus signal, the CAN transceiver converts the signal level into a logic state, that is, after the CAN_H and CAN_L levels are subtracted, an interpolation level is obtained. Various disturbances have the same effect on the two wires, and the subtracted interpolated level can filter these disturbances.

6. DMA

DMA refers to the interface technology that external devices directly exchange data with the system memory without going through the CPU. The transfer speed of such data depends on the working speed of memory and peripherals.

Usually the system bus is managed by the CPU. In the DMA mode, it is hoped that the CPU will give up these buses, that is, the lines connected to these buses by the CPU are in the third state (high-impedance state), and the DMA controller takes over and controls The number of bytes transferred, determine whether the DMA is over, and send out the DMA end signal.