The English full name of SPI is Serial Peripheral Interface, which as the name suggests is a serial peripheral interface. SPI is a synchronous serial communication interface specification, which is mainly used for short-distance communication in embedded systems. The interface was developed by Motorola in the mid-1980s and has since evolved into an industry specification.
The communication between SPI devices adopts full-duplex mode, which is a master-slave mode of a master and one or more slaves. The host is responsible for the initialization frame. This data transfer frame can be used for both read and write operations. The chip select line can select one from multiple slaves to respond to the host's request.
For multiple slave devices, each slave needs a CS/SS line to connect to the host, so that the host can communicate with any slave. As shown in the figure below, it is the connection method of one master and multiple slaves.

Most slave devices feature tri-state logic, so when the device is unselected, their MISO signal lines become high impedance (electrically disconnected). Devices without tri-state outputs need an external tri-state buffer to share the SPI bus with other slave devices.

data transmission
In SPI communication, the SPI master device sends the SPI slave device through the SCLK line at the frequency supported by the slave device, which also means that the slave cannot actively send data to the master, but the master can only poll the slave to send data to the slave. Or the slave device actively informs the host of the arrival of data through an IO port.
In each clock cycle of SPI, a full-duplex data transmission is performed. When the master sends 1bit through the MOSI line, the slave will also send 1bit of data through the MISO line after reading it. This means that this communication order is maintained even if only simplex communication takes place.
SPI transfers usually involve two shift registers of a given word length. For example, an 8-bit shift register in the master and slave. They are connected in a virtual ring topology, with data usually being shifted out most significant bit first. On the clock edge, both the master and the slave shift out 1 bit of data from the transmission line to each other. When the next clock edge arrives, the receivers on both sides sample the bit on the transmission line and set it as the new least significant bit of the shift register. After register bits are shifted out and in, the master and slave exchange register values. If more data needs to be swapped, reload the shift register and repeat the process. A transfer can last for any number of clock cycles. When done, the host stops toggling the clock signal.