The CAN bus is a multi-master broadcast differential serial bus. Its core relies on differential transmission at the physical layer, non-destructive arbitration at the data link layer, and end-to-end error checking to achieve masterless coordination and highly reliable real-time communication among multiple nodes. It operates in two core steps: the physical layer and the data link layer, containing complete transmit/receive, arbitration, and fault-tolerant logic.

I. Physical Layer: Foundation of Signal Transmission (Core of Interference Resistance)

The physical layer defines the bus hardware connections and electrical characteristics, determining signal transmission stability and adapting to harsh electromagnetic environments such as automotive environments.

1. Hardware Composition: The core consists of CAN_H (high-level line) and CAN_L (low-level line) twisted-pair cables, paired with a CAN controller (protocol conversion) and a CAN transceiver (level conversion). Both ends of the bus require 120Ω terminating resistors (to match the characteristic impedance of the twisted-pair cable, eliminate signal reflection; one end can be omitted for short distances <1m). 2. Signal Level Definition: Logic states are distinguished by the voltage difference between the two lines, providing extremely strong immunity to common-mode interference.

Dominant Level (Logic 0): CAN_H≈3.5V, CAN_L≈1.5V, voltage difference 2V, higher priority than recessive level, can cover recessive signals;

Recessive Level (Logic 1): CAN_H and CAN_L both≈2.5V, voltage difference close to 0V, representing the bus idle state.

3. Transmission Rate and Distance: Rate and distance are inversely proportional, adapting to different scenarios.

High-Speed CAN (ISO11898): 125Kbps~1Mbps, maximum distance ≤40m (at 1Mbps), suitable for core automotive control (e.g., engine, brakes);

Low-Speed CAN (ISO11519): 10~125Kbps, maximum distance up to 1000m, suitable for vehicle auxiliary equipment (e.g., windows, lights).

4. Transmit/Receive Level Conversion

Transmit: CPU signal → CAN controller converts to logic level (0/1) → CAN transceiver converts to differential level (CAN_H/CAN_L voltage difference) → Bus transmission;

Receive: Bus differential level → CAN transceiver converts to logic level → CAN controller parses → Signal transmitted to CPU.

II. Data Link Layer: Data Transmission and Arbitration (High-Efficiency Real-Time Core)

Responsible for data encapsulation, bus contention, and error checking. Its core features are "non-destructive arbitration" (no data loss) and "short frame structure" (high real-time performance).

1. Core Frame Types (Primarily Data Frames, Accounting for 90%+ of Communication)

CAN frames are divided into 5 categories, each with different functions. Data frames are the core data carrier:

Data Frames: Actively transmit user data, including standard frames (11-bit ID) and extended frames (29-bit ID), adapting to different priority requirements;

Remote Frames: Request other nodes to send specified data, have no data field, and have lower priority than data frames with the same ID;

Error Frames: Sended by a node when an error is detected, notifying the entire bus to avoid data anomalies;

Overload Frames: Sended when the bus load is too high, requesting a reduction in the communication rate;

Frame Interval: Separates different frames to avoid signal superposition and interference.

2. Complete Data Frame Structure (Standard Frame, 44 bits)

Divided into 7 segments in sequence, each segment has a specific function to ensure data integrity and traceability:

1. Start Bit (1 bit): Dominant level (0), marks the start of the frame, synchronizes the clocks of all nodes;

2. Arbitration Field (12 bits): Includes 11-bit ID (priority identifier, the smaller the value, the higher the priority) + 1 RTR bit (0 for data frames, 1 for remote frames), the core segment for arbitration;

3. Control Field (6 bits): 1 reserved bit + 4-bit DLC (Data Length Code, 08 bytes, specifies the length of the data field); 4. Data Field (064 bits): Actual transmitted data. Short frame design (maximum 8 bytes) reduces interference, improves real-time performance, and is suitable for automotive control scenarios.

5. CRC Field (16 bits): 15-bit Cyclic Redundancy Check (CRC) code + 1-bit delimiter. The receiving end recalculates and verifies the data to detect transmission bit errors.

6. Acknowledgment Field (2 bits): 1 ACK slot + 1 delimiter. After the receiving node verifies the data correctly, it sends a dominant level (0) in the ACK slot to acknowledge the transmission. The sending end detects this and considers the transmission successful.

7. End Bit (7 bits): Recessive level (1), indicating the end of frame transmission.

3. Non-destructive arbitration mechanism (conflict-free bus)

When multiple nodes transmit data simultaneously, priority is determined by comparing IDs bit by bit, ensuring no data loss. This is the core of CAN's real-time performance:

1. When the bus is idle, any node can initiate transmission, synchronously transmitting bit by bit starting from the start bit;

2. All transmitting nodes monitor the bus level in real time, comparing their own transmitted level with the actual bus level;

3. If a node transmits a recessive level (1), but detects a dominant level (0) on the bus, it indicates the existence of a higher-priority node. Transmission is immediately stopped, and the node switches to receive mode (no data loss; retrying after the bus becomes idle);

4. Ultimately, only the highest-priority (smallest ID) node continues transmitting, completing the entire frame transmission. Other nodes wait to retry, with no data conflict or damage throughout the process.

4. End-to-End Error Detection and Fault Tolerance (High Reliability Guarantee)

5-fold error detection mechanism, combined with an error counter, to prevent the propagation of abnormal data:

1. Bit Monitoring: The transmitting node compares its own transmitted level with the actual bus level; if they are inconsistent, an error is determined.

2. Bit Stuffing: From the start of the frame to the CRC segment, after 5 consecutive identical levels, a reversed level is inserted. The receiver automatically removes this, preventing clock synchronization issues. Six consecutive identical level errors are detected.

3. Frame Format Check: The start bit, end bit, delimiter, and other fixed formats are verified; if they do not match, an error is determined.

4. CRC Check: The receiver recalculates the CRC value and compares it with the CRC code within the frame; if they are inconsistent, an error is determined.

5. Missing ACK: If the transmitting end does not detect a dominant ACK slot level, reception is considered a failure, triggering a retransmission.

6. Error State Management: Each node contains a transmit/receive error counter. The state switches according to the error frequency (error active → error passive → bus shutdown). Nodes shutting down the bus suspend communication to prevent the entire bus from being overwhelmed.

III. Overall Communication Flow (Complete Single-Frame Data Link)

1. Node 1 (high-priority ID) initiates transmission, encapsulating the data into a data frame, which is then converted into a differential signal by the CAN controller and transceiver, and transmitted via CAN_H/CAN_L;

2. All nodes on the bus receive the differential signal, convert it to logic level, and parse the frame structure, first verifying the start bit to synchronize the clock;

3. If Node 2 (low-priority ID) is also transmitting simultaneously, the arbitration field ID is compared bit by bit. If Node 2 detects that the dominant level on the bus is covering its own recessive level, it stops transmitting;

4. Node 1 completes the transmission of the entire frame. The receiving node verifies the CRC and frame format. If the verification is correct, an acknowledgment signal is sent to the ACK slot;

5. Node 1 detects the ACK confirmation, and the transmission is complete; if no ACK is detected, a retransmission is triggered. If multiple failures occur, the error counter switches the state.