Low-Power Sleep Modes: Deep Sleep vs Light Sleep

Key Takeaways

• Deep sleep loses RAM and register state, so the part restarts from reset on every wake.
• Light sleep keeps RAM and registers powered, so execution resumes at the next instruction.
• Light sleep draws more current than deep sleep because the retained domain keeps leaking.
• Average current, not sleep current, decides battery life for a duty-cycled node.
• A restart is acceptable when the wake interval is long and the firmware can reload its state.

1. What Is Deep Sleep?

Deep sleep is a low power mode that powers down most internal domains, loses RAM and register state, and restarts from reset on wake.

• Power domains are switched off. The core, the radio and most peripherals lose supply or clock, so leakage falls to the retained domain. Anything held in a volatile register is gone.
• State is lost by design. RAM and register values are not preserved, so execution begins again from the reset vector rather than from the sleep call. Firmware treats wake as a cold start with a reason code.
• Wake sources are limited. A deep sleep part typically wakes from an external pin, a wake timer or a radio interrupt, and no other event can bring it back.
• Start-up cost repeats. Clock start-up, oscillator settling and peripheral re-initialisation are part of every wake, so the latency is paid on each cycle.

2. How Does Deep Sleep Work?

A deep sleep cycle is a fixed sequence, and each step has a firmware consequence.

1. Decide what must survive. The firmware identifies values needed after wake, such as counters or calibration, and writes them to non-volatile storage before sleeping.
2. Quiesce the peripherals. The radio enters its own low power state, the UART and ADC are disabled, and each GPIO is set to a defined level.
3. Switch the domains down. High-speed clocks stop and power is removed from most of the die, leaving the wake logic and a low-frequency timer.
4. Wake from a permitted source. An external pin, the wake timer or a radio interrupt restarts the part, and a status register reports which one fired.
5. Re-initialise and report. Clocks restart, peripherals are configured again, stored state is read back, and the node performs its scheduled work.

3. What Is Light Sleep?

Light sleep is a low power mode that stops the clock while keeping supply and RAM powered, so execution resumes at the next instruction.

• Clocks stop, memory stays. The processor halts and busy peripherals are gated, but supply and RAM remain powered, so registers and stack contents are intact.
• Wake returns to the same place. The program counter continues from the instruction after the sleep call, with no reset and no re-initialisation path.
• Wake is nearly immediate. Any enabled interrupt returns the part, including a UART start bit, a GPIO edge or a timer compare, so latency is microseconds.
• Leakage sets the floor. Current is higher than in deep sleep because the retained domain still leaks, dominated by RAM retention, the RTC and the regulator.

4. Deep Sleep vs Light Sleep: What Is the Difference?

Deep sleep and light sleep differ in what they retain, not in their intent to save power.

The decision rule: choose deep sleep when the wake interval is long and the node can rebuild its state from scratch; choose light sleep when events arrive often enough that a restart on each one would cost more than the retention current.

5. Low Power Sleep: Configuration and Key Parameters

Every figure below has to be measured on the finished board, because the module is one term in the sum.

• Sleep current in the microamp region: quoted under stated conditions, such as 2 uA for the E22-400T22D-V2 and 12 uA hibernate for the E103-W03.
• Average current over the duty cycle: sleep current plus active current weighted by duty cycle; lowering the first while lengthening the second does not lower the average.
• Wake latency: time from the wake event to the first useful instruction, including start-up in deep sleep. Treated as zero, it makes timed protocols miss their reply window.
• RTC and its clock source: the wake timer keeps time while the core is off, so its accuracy sets how far the sleep interval drifts.
• RAM retention and its leakage: retention keeps state alive in light sleep and forms the largest term in retained current.
• GPIO leakage from a driven input: a pin held mid-level, or an external pull-up fighting an internal pull-down, conducts continuously.
• Regulator quiescent current: left in a high-performance state, the regulator becomes the dominant load and the module figure stops mattering.
• Decoupling and inrush at wake: the wake transient pulls a pulse from the decoupling network; too little capacitance drops the rail and resets the part.
• Brown-out on a weak cell: the threshold must sit above the wake transient and below the cell end-of-life voltage.

6. When to Use Deep Sleep and When to Use Light Sleep

Good fit

• Nodes that report on a schedule, where the interval is minutes to hours and a restart costs nothing.
• Sensor endpoints that read one value, transmit and sleep, with no session to maintain.
• Designs where firmware can rebuild state from non-volatile storage or from the network on each wake.
• Event-driven endpoints that must react quickly to a button, an alarm input or an inbound radio frame, using light sleep.

Poor fit

• Hosts that must answer inside a window shorter than the start-up time of deep sleep.
• Applications that keep a live connection, with session buffers held in RAM.
• Rapid sampling loops, where the deep sleep wake overhead exceeds the time spent measuring.
• Nodes with very long sleep intervals, where retained current in light sleep outweighs the saving in wake time.

7. Real-World Applications

In asset tracking, utility metering and building sensing, an endpoint measures on a timer, transmits over a low power radio, and returns to sleep. Whether that sleep is deep or light decides battery life, the wake path and how much state the firmware has to persist.

Ebyte modules expose both behaviours through their own sleep and wake features. The E22-400T22D-V2 is a Semtech SX1268 LoRa UART module covering 410.125-493.125 MHz at 22 dBm, with a listed 2 uA sleep current and a 2.3-5.5 V supply, and it supports wake-on-radio, so an incoming packet can bring a sleeping node back without a host timer. The E103-W03 is a serial-to-Wi-Fi module based on the TI CC3220R SoC with a 12 uA hibernate sleep current and AT command support.

For Zigbee designs, the E180-Z5812SP and E180-Z5812SX use Telink TLSR8258 parts at 2.4 GHz with a 32-bit MCU up to 48 MHz, so the application runs on the module and an endpoint can use its own interrupts instead of a host. Where a smaller node is needed, the E104-BT5010A is a serial-to-BLE 5.0 module based on the Nordic nRF52810 in an 11.5 x 16 mm package with 3.8 dBm output.

8. FAQ: Sleep Modes in Practice

Q1: What is the difference between deep sleep and light sleep?

Deep sleep removes power from most of the die and loses RAM, so the part restarts when it wakes. Light sleep stops the clock but keeps RAM and registers powered, so execution continues at the next instruction. The trade is wake latency and firmware complexity against sleep current.

Q2: How much sleep current does a low power node draw in each mode?

Sleep current for a low power node is usually in the microamp region once the radio, regulator and GPIOs are handled. Vendor figures are quoted under stated conditions, such as 2 uA for the E22-400T22D-V2 and 12 uA hibernate for the E103-W03. Board leakage is added by the designer.

Q3: Which wake sources work with deep sleep and with light sleep?

Light sleep wakes from any enabled interrupt, such as a timer compare, a GPIO edge or a UART start bit, and returns in microseconds. Deep sleep wakes from a smaller set, typically an external pin, a wake timer or a radio interrupt. Light sleep suits events that must be answered quickly.

Q4: Is a restart from deep sleep a problem for my firmware?

A restart is fine when the node samples, transmits and sleeps, because no state is worth keeping. It becomes a problem when the firmware holds a connection, a calibration table or a counter that takes time to rebuild. Those values must be written to non-volatile storage before the part sleeps.

Q5: How do I budget average current for a duty-cycled battery node?

Average current is the sleep current plus the active current weighted by the duty cycle. A node that wakes for 100 ms at 20 mA once every 10 minutes adds roughly 3.3 uA to the average. Measure both terms before promising a battery life figure.

Q6: Why is my battery node still draining fast in sleep mode?

A measured sleep current far above the module figure almost always comes from the carrier board, not the module.

• Sleep current high with the module fitted -> remove the module and measure again, because a pull-up, LED or sensor can dominate.
• Current rises after the first wake -> check that every peripheral and GPIO returns to its sleep configuration at the end of the cycle.
• Drain appears with a weak cell -> check the regulator and brown-out threshold, since the wake transient can reset the part.

9. Pre-Flight Checklist Before You Choose a Sleep Mode

1. List the values that must survive a wake, and confirm each one is written to non-volatile storage when the chosen mode is deep sleep.
2. Measure sleep current on the assembled board with the module fitted, then again with it removed, so board leakage is separated from module behaviour.
3. Compute average current from both the sleep and active terms over a realistic duty cycle, including the wake transient, before quoting a battery life figure.
4. Check that each wake source the product depends on is supported in the chosen mode, and that the required response time is longer than the wake latency.
5. Verify that the GPIO and regulator states left behind by the sleep path match the configuration the firmware assumes when it wakes.