Bit Synchronization vs Frame Sync in Serial Links

• Bit synchronization recovers the bit clock from each start bit; frame synchronization decides where a message begins and ends.
• With 16-times oversampling, a receiver tolerates roughly 2 to 3 percent clock mismatch per character.
• Clock error accumulates inside one character, so timing faults scale with character length, not cable length.
• Frame synchronization uses other clues: a silent interval, a preamble plus sync word, a length field or an address filter.
• Bit-level faults corrupt single characters; frame-level faults reject whole packets despite otherwise valid bits.

1. What Is Bit Synchronization?

Bit synchronization is how a receiver recovers the transmitter's bit clock from the data stream and samples each bit at the right instant.

On an asynchronous link there is no clock conductor. The receiver runs free while the line is idle and re-derives timing from the falling edge of every start bit, which becomes the phase reference for the whole character.

Core characteristics

• Phase from the edge, frequency from a local oscillator: the start bit says when to sample, but the spacing comes from the receiver's own clock, so a 2 percent error at one end is a 2 percent error in every bit position.
• Accuracy matters only cumulatively: the first data bit is nearly always sampled correctly, and the last one is where margin disappears.
• Resynchronisation is free and constant: framing restarts with each character, so timing never drifts across a message; a long gap is a fresh start, not a re-acquisition problem.
• It stays hidden until it fails: no status flag reports marginal timing, so the evidence is corrupted characters and framing errors that come and go.

2. How Does Bit Synchronization Work on an Asynchronous Link?

An asynchronous receiver rebuilds timing from scratch for every character.

1. Idle line and receiver arming. The line rests in the mark state and the receiver watches for the opposite level; any disturbance holding it low long enough is accepted as a start bit, so a floating input produces phantom characters.
2. The falling edge is the timing reference. In a standard asynchronous serial receiver with 16-times oversampling, that edge is detected and the internal counter is reset; nothing before it carries timing information.
3. Sampling at bit centres with multiple-times oversampling. The receiver counts a fixed number of local ticks per bit and samples each bit at its centre; with 16-times oversampling it votes on three samples there.
4. Resynchronisation on every start bit. Because the counter is reloaded for each character, clock error cannot accumulate across a packet - only from the start edge to the last sampled bit.
5. Why error accumulates inside the character. Each bit position slips by the fractional error of one bit period. In 8-N-1 framing, 10 bit periods separate the start edge from the stop bit, so a 2 percent mismatch moves that sample about 0.2 bit periods from centre.
6. What that means for the design. Choose a clock source more accurate than the margin you need, and check it across temperature.

3. What Is Frame Synchronization?

Frame synchronization is how a receiver decides where one message begins and ends, and therefore which bits belong together as a single frame.

Bit synchronization works character by character; frame synchronization works on groups of characters, and a link can have excellent bit timing while still failing here.

1. Silent-interval framing on a Modbus RTU bus. Per the Modbus over Serial Line specification, a frame is delimited by an idle period of at least 3.5 character times. There is no header, so a converter that re-buffers or splits the byte stream merges or splits frames.
2. Preamble and sync word in a packet radio. A burst opens with an alternating-bit preamble that lets the demodulator settle its bit clock and gain control, then a fixed sync word to correlate against.
3. Length fields and address filters. Many formats follow the sync word with a destination address and a length byte; the filter discards other nodes' frames and the length byte defines the frame end.
4. How a false sync is rejected. A random pattern can match the sync word by chance, so receivers combine a correlation threshold, an address check and a checksum before passing it up.
5. What that means for the design. The framing rule must match end to end; if one end relies on inter-frame silence and the other expects a sync word, no bit-level tuning will help.

4. Bit Synchronization vs Frame Synchronization: What Is the Difference?

Bit synchronization aligns a receiver to individual bits; frame synchronization aligns it to whole messages, and different mechanisms solve them at different layers.

The decision rule: when single characters are wrong, fix bit timing first; when the bytes look right but the messages are wrong, stop tuning the baud rate and fix the framing rule instead.

5. Configuration and Key Parameters That Decide Timing

The parameters below change timing behaviour in the field and each fails in a recognisable way.

• Baud rate and tolerance between the two ends: 9600 to 115200 bps is typical, with roughly 2 to 3 percent total mismatch as the practical limit; errors then grow with character length and temperature.
• Data bits, parity and stop bits: 8-N-1 is the common default; 7-E-1 or two stop bits widen the accumulation window, and a mismatch gives steady framing errors.
• Oversampling factor: 16-times with a three-sample majority vote is typical; 8-times or single-sample detection saves power but loses filtering.
• Air data rate versus UART baud rate on a radio module: the air rate sets time on air; feed the UART faster than the air carries bytes and the transmit buffer overruns.
• Preamble and sync word length: a longer preamble lets the demodulator settle before the first data bit; too short a preamble appears as partial frames.
• Inter-frame gap on a Modbus RTU bus: at least 3.5 character times of silence; too short a gap splits one frame, while a path that destroys the gap merges two.
• Receive-buffer and DMA latency versus frame gap: the host must read bytes before the next frame starts, or the overrun flag drops data.
• Start-up time of a transceiver before the first bit: transmit enable and modulator ramp-up take time, so writing immediately after enabling the driver clips the first bytes.

6. When Each Layer of Synchronisation Fits, and When It Does Not

Good fit for bit synchronization by clock recovery

• Point-to-point links where both ends run from a crystal reference, keeping mismatch in the hundreds of parts per million.
• Slow to medium baud rates, where a fixed absolute timing error is a smaller fraction of the sample window.
• Links with a defined preamble, because the training period lets the demodulator settle before the first data bit.

Poor fit for relying on bit synchronization alone

• Very high baud rates over long cable, where cable rise time eats the narrowed sample window.
• Designs clocked from an internal RC oscillator across a wide temperature range, unless the baud rate is reduced.

Good fit for frame synchronization by delimiter

• Modbus RTU buses, where the silent interval is part of the specification, and packet radios, where a preamble plus sync word opens each burst.

Poor fit for frame synchronization by silent interval

• Through a converter, gateway or cellular modem that re-buffers data, unless transparent forwarding with bounded latency is guaranteed.
• On a bus with a permanently chatty node, because continuous traffic leaves no gap to detect.

7. Real-World Applications

In telemetry and building control the two tasks sit in different parts of one system: the host MCU handles bit timing, while the radio, the Modbus stack or the gateway decides where frames begin and end.

Ebyte modules show the split. The E22-400T22D-V2, built on the SX1268, is a 410.125-493.125 MHz LoRa UART wireless module with TTL UART output compatible with 3.3 V and 5 V IO, an adjustable 22 dBm output and up to 5 km of open-air line-of-sight range; preamble and sync word handling stay inside the module. The E220-400T30S, powered by the Semtech LLCC68, supports both LoRa and FSK modulation with a 30 dBm (1 W) option. For slow links the E30-433T20D pairs a Silicon Labs SI4463 with UART communication supporting 1200-115200 baud and -121 dBm sensitivity at 5 kbps.

At packet level, the E70-433T14S2 is a TI CC1310F64RSM transceiver with GFSK modulation, 431-446 MHz operation, 14 dBm output, -108 dBm receive sensitivity, hardware forward error correction and 1.5 km range; the FEC absorbs the bit errors an air link produces. The E01-ML01S, based on the nRF24L01P, offers SPI and air data rates up to 2 Mbps, leaving frame synchronisation to address filtering.

On the wired side, the MA01-AACX2220 is an RS485 Modbus RTU I/O module with two digital inputs, two analogue inputs and two relay outputs, and it depends on the 3.5-character silent interval for its frame boundaries. The ME31-AXXX8000, an 8-way dry contact Modbus gateway supporting Modbus TCP or Modbus RTU, translates between TCP stream framing and RTU gap framing, so gateway latency is a timing parameter. The E840-DTU(EC05-485)E-V2 industrial LTE Cat-1 RS485 modem carries serial data transparently over TCP, UDP, MQTT or HTTP, so the inter-frame gap must survive the mobile network, while the compact E108-GN02 GNSS module outputs NMEA0183 v4.1 sentences delimited by protocol characters rather than a silent interval.

On radio links the antenna and its feed line set the signal-to-noise ratio the demodulator works with, so a poor match turns a healthy bit error rate into frequent frame rejections.

8. FAQ: Bit and Frame Synchronisation in Practice

Q1: What is the difference between bit synchronization and frame synchronization?

Bit synchronization aligns the receiver to each individual bit, using the start bit and oversampling. Frame synchronization decides where a message begins and ends, using a silent interval, a preamble plus sync word, or a length field. They are separate layers with separate failure modes.

Q2: How much baud rate mismatch can a UART tolerate?

Roughly 2 to 3 percent total mismatch between the two ends in a standard receiver with 16-times oversampling. Beyond that, the last data bits are sampled outside their window and framing errors appear intermittently. Crystal sources stay inside that budget.

Q3: Why does my serial link work at 9600 baud but fail at 115200 baud?

Because clock error accumulates inside one character, and at a higher baud rate the absolute sample window narrows even though the fractional slip stays the same. Cable rise time, receiver latency and marginal signal edges consume the remaining margin, so the link fails intermittently.

Q4: What is a preamble and sync word in a wireless module?

A preamble is a run of alternating bits that gives the receiver time to settle its bit clock and gain control before payload arrives. The sync word is a fixed pattern the receiver correlates against to mark the first bit of a frame. A mismatched sync word produces silence.

Q5: Why does my Modbus RTU converter merge or split packets?

Because the receiver depends on the inter-frame silent interval and the converter re-buffers or splits the byte stream, destroying that timing. Per the Modbus over Serial Line specification a frame is delimited by at least 3.5 character times of silence.

Q6: The radio link receives nothing or only part of each packet - what should I check?

Check framing, power and timing, in that order.

• Receives nothing at all → verify that sync word, address filter, channel and air data rate match at both ends.
• First bytes intact, then truncation → check preamble length and transceiver start-up time.
• Short packets fine, long packets fail → compare buffer and DMA latency against the frame gap.

9. Practical Checklist Before You Change Any Timing Parameter

1. Classify the fault before touching a setting. Corrupted characters point to bit timing; merged, split or missing packets point to framing.
2. Verify the clock budget at both ends. Check oscillator accuracy across the full temperature range and keep mismatch inside roughly 2 to 3 percent.
3. Confirm the framing mechanism on both sides. Gap timing, sync word or length field must be the same rule end to end; a mismatch cannot be tuned away at the baud rate.
4. Measure the inter-frame gap after any converter. Confirm the silent interval reaches the far end intact and that added latency stays below one frame period.
5. Check the antenna and the ground reference last. Signal quality reduces bit errors, and a poor match shows up as frame rejections.